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Phase 3: display, msm DRM drives the eDP panel (2026-11-03)

Attempt 2026-11-03-4. Image ab87e567a0eb05bd, kernel #5 (2026-11-03 2:09 PM ET), commit 072f347. Sources: the netlog dumps/firstboot/2026-11-03-netlog.txt and the AP console log dumps/firstboot/2026-11-03-ap.log (both gitignored), plus the owner looking at the panel.

Why

Every earlier boot went dark at about 33 s: VREG_EDP_3P3: disabling (attempt 2026-11-03-3, wifi-2026-11-03.md). The mica DTS already described the mainline display path (&mdss, &mdss_dp3 with an edp-panel on its aux-bus, &mdss_dp3_phy, vreg_edp_3p3, pwm-backlight), matching the stock sde_edp (entry01-overlay.dts fragment 11). But every driver on it was =m in defconfig at a804c57, and the initramfs loads no modules. Only simpledrm drove the screen, nothing claimed the panel supply, and the regulator core turned it off as unused.

Changes (commit 072f347)

  • kernel/mica-display.config: DRM_MSM, PHY_QCOM_EDP, CLK_X1E80100_DISPCC, DRM_PANEL_EDP, BACKLIGHT_CLASS_DEVICE, BACKLIGHT_PWM and LEDS_QCOM_LPG set =y, plus the dependency chain: QCOM_LLCC and QCOM_OCMEM (DRM_MSM=y needs them =y or =n), and LEDS_CLASS_MULTICOLOR and QCOM_PBS for the LPG.
  • Command line: msm.skip_gpu=1. Otherwise the GPU would join the MDSS component match (msm_drv.c:1076-1086) and wait on gpucc, whose SMMU 3da0000.iommu is still deferred.
  • DTS: the backlight’s edp_bl_en pin state moves from TLMM 74 (left over from the 9345; stock muxes it to QUP SE18) to PMC8380-3 GPIO 4, the stock qcom,edp-backlight-en-gpio. The PWM pin takes the stock edp_pwm_active config.
  • /init: DRM connectors, the backlight, the panel supplies after uptime 40 s, the panel identity from the EDID (no serials; check.sh test 16), display dmesg, and a banner on tty1.

Result: pass

The panel stayed lit past 40 s and showed the GBOOK: display check banner (the owner saw it).

  • msm binds early:
    • [drm] Initialized msm 1.13.0 for ae01000.display-controller on minor 1 at 1.154 s.
    • dpu hardware revision:0x90020000.
    • All three DP controllers bound (ae90000, ae98000, aea0000).
    • fb0: msmdrmfb frame buffer device at 1.595 s, taking over from simpledrm’s fb0 (0.453 s).
    • no GPU device was found: expected with msm.skip_gpu=1.
  • Connectors: card1-eDP-1 status=connected enabled=enabled modes=2560x1600. card1-DP-1 and card1-DP-2 are disconnected (nothing on Type-C), and card1-Writeback-1 is there too.
  • Panel supply: VREG_EDP_3P3 state=enabled users=1 and VBL9 state=enabled users=1 after 40 s. No VREG_EDP_3P3: disabling line this boot.
  • Backlight: backlight max=4095 actual=2048 power=0, a 12-bit PWM at 50 %. Stock caps the level at 0x190 (fragment 11) and 0x200 (fragment 77); mainline uses the LPG’s full range.
  • Panel: Unknown panel LGD 0x0804, using conservative timings. That’s LG Display, product 0x0804, not in edp_panels[] at a804c57. The WARN_ON splat at panel-edp.c:829 is the driver’s deliberate “add a table entry” signal (comment at :824-828), not a fault. Conservative timings only lengthen the power sequencing delays.
  • Deferred at the end: only arm-scmi (mailbox 17430000). 3da0000.iommu was listed at the first check and not at the last.

Not yet captured

  • GBOOK: panel-id=card1-eDP-1 none: sysfs reports the edid attribute’s size as 0, so [ -s ] skipped a readable file. Fixed in commit 2d2f2b5 (test -r; none on a short read). The next image will print the EDID name and text descriptors.
  • The dropbox readback (attempt.sh readback) didn’t run because adb was down after the stock boot (Wireless debugging). Netlog has the whole log, so nothing is missing.

Next for display

  1. Add an edp_panels[] entry for LGD 0x0804. It needs the panel’s datasheet delays; the EDID name from the next image identifies the part. This is for upstream; the panel works without it.
  2. External DP over Type-C (mdss_dp0/dp1 are bound; aux_bridge still reports “failed to acquire drm_bridge” in usb-2026-11-02.md).
  3. The GPU: CLK_X1E80100_GPUCC=y (unblocks 3da0000.iommu), drop msm.skip_gpu=1, and stage the GPU firmware. Zap is off under EL2.